1. Field of the Invention
The present invention relates to a semiconductor integrated circuit apparatus that incorporates a variety of functions, and more particularly to data transfer between function blocks within a system LSI (Large Scale Integration) suitable for low-power-consumption implementation using Adaptive Voltage Scaling technology.
2. Description of the Related Art
With the level of semiconductor integration continuing to quadruple every three years for more than 10 years, the scale of semiconductor integrated circuits has become immense, and major changes have also been made in the approach to semiconductor integrated circuit chip configuration.
FIG. 1 is a block diagram showing the configuration of a system LSI.
In FIG. 1, a semiconductor integrated circuit apparatus 10 is configured by means of a general-purpose CPU 11, a DSP (Digital Signal Processor) 12, a dedicated circuit 13 (dedicated circuit <1>), a dedicated circuit 14 (dedicated circuit <2>), an SDRAM (Synchronous Dynamic RAM) access control circuit 15, a DMA (Direct Memory Access) controller 16, and so forth, which are interconnected via a common bus 17. CPU 11 and DSP 12 have internal memory 11a and 12a respectively. This semiconductor integrated circuit apparatus 10 is normally provided with large-capacity external SDRAM 18, and is used in a Unified Memory configuration.
Even at present there is a possibility of demands concerning functions incorporated in a semiconductor integrated circuit changing in whirlwind fashion from day to day, and if some functions are configured in the manner of dedicated circuit <1> and dedicated circuit <2> as shown in FIG. 1, it may not be possible to respond promptly to such desired changes.
Consequently, there is currently an ongoing trend of using a so-called [multifunction DSP+extension function] configuration for functions centered on computational functions other than those of a general-purpose CPU, and providing for specifications that may possibly change by means of software in the multifunction DSPs, as shown in FIG. 2.
FIG. 2 is a block diagram showing another configuration of a system LSI. Configuration elements identical to those in FIG. 1 are assigned the same codes as in FIG. 1.
In FIG. 2, a semiconductor integrated circuit apparatus 20 is configured by means of a general-purpose CPU 11, a computational function section 23 comprising a multifunction DSP 21 (multifunction DSP <1>) and extension function 22 (extension function <1>), a computational function section 26 comprising a multifunction DSP 24 (multifunction DSP <2>) and extension function 25 (extension function <2>), an SDRAM control circuit 15, a DMA controller 16, local buses 27 through 29 located on the function block side, a global bus 30 located on the SDRAM control circuit 15 and DMA controller 16 side, and bus bridges 31 through 33 that connect local buses 27 through 29 to global bus 30. Multifunction DSP 21 (multifunction DSP <1>) has internal memory 21a. In the bus configuration, local buses 27 through 29 are assigned to the respective function blocks, global bus 30 is located on the SDRAM control circuit 15 side, and bus bridges 31 through 33 are located between local buses 27 through 29 and global bus 30.
As more and more functions become incorporated in semiconductor integrated circuits in line with future advances in semiconductor processes, the configuration of semiconductor integrated circuit apparatuses can be expected to change further in the manner illustrated in FIG. 3.
FIG. 3 is a block diagram showing yet another configuration of a system LSI. Configuration elements identical to those in FIG. 2 are assigned the same codes as in FIG. 2.
In FIG. 3, a semiconductor integrated circuit apparatus 40 is configured by means of one general-purpose CPU 11, a plurality of (here, four) general-purpose computational processors 41 through 44 that have internal memory 41a through 44a respectively, an SDRAM control circuit 15, a DMA controller 16, an I/O control circuit 45 that controls a peripheral I/O group 60, a local bus 46 located on the CPU 11 and I/O control circuit 45 side, local buses 47 through 50 located on the general-purpose computational processor 41 through 44 side, a global bus 51 located between local bus 46 and local buses 47 through 50, bus bridges 52 through 55 that connect local buses 47 through 50 to global bus 51, and a bus bridge 56 that connects local bus 46 to global bus 51.
Thus, in this semiconductor integrated circuit apparatus 40, one CPU 11 and a plurality of (from four to eight or so) general-purpose computational processors 41 through 44 are connected to local buses 46 through 50 and global bus 51 via bus bridges 52 through 56, large-capacity SDRAM 18 is located externally, and SDRAM control circuit 15 performs SDRAM 18 arbitration with CPU 11, general-purpose computational processors 41 through 44, DMA controller 16, and so forth.
The most serious problem when the level of integration of a semiconductor integrated circuit apparatus is raised as described above is increased power consumption during operation and in standby mode. The technologies receiving the greatest attention as means of solving this problem are Dynamic Voltage Scaling (DVS) and Adaptive Voltage Scaling. Details of these technologies are given in the documents below (for example, Documents 1 and 2, and Non-patent Documents 1 and 2), and therefore a description of these technologies is omitted here. Document 1 is the Specification of U.S. Pat. No. 5,745,375, and Document 2 is the Specification of U.S. Pat. No. 6,868,503. Non-patent Document 1 is “A Combined Hardware-Software Approach for Low-Power SoC: Applying Adaptive Voltage Scaling and Intelligent Energy Management Software”, Design 2003 (System-on-Chip and ASIC Design Conference), and Non-patent Document 2 is “An H.264/MPEG-4 Audio/Visual Codec LSI with Module-Wise Dynamic Voltage/Frequency Scaling”, ISSCC2005 Dig. Tech. Papers, pp. 132-133.
However, the following kinds of problems have been associated with such conventional semiconductor integrated circuit apparatuses.
According to above Non-patent Document 1, there are at present major limitations in Adaptive Voltage Scaling technology. With current Adaptive Voltage Scaling technology, use of this technology for an entire chip is presupposed. In this case, the entire chip changes its power supply voltage and the corresponding system clock frequency simultaneously. That is to say, in this system, the chip's power supply voltage and system clock frequency vary on the time axis, and when the amount of additional work is large, the CPU performs control so that the chip's power supply voltage is raised (for example, VDD=1.5 Volt) and the system clock frequency is also raised (for example, fclk=400 MHz). Also, when the workload becomes smaller, the CPU performs control so that the chip's power supply voltage is lowered (for example, VDD=1.0 Volt) and the system clock frequency is also lowered (for example, fclk=200 MHz). By so doing, the power consumption expended by this chip can be reduced.
However, this system is not practical. As described above, there are normally various kinds of function blocks in a system LSI, such as a video signal processing block, an audio signal processing block, and a control signal processing block, and furthermore, the workload necessary for this processing varies greatly among these function blocks.
The prior art that attempts to solve this problem includes above Non-patent Document 2. Here, the power supply voltage of the audio signal processing block can be selected from 0.9 V or 1.2 V, and the system clock frequency from 90 MHz or 180 MHz, while the power supply voltage and system clock frequency for blocks other than the audio signal processing block (including a video signal processing block and so forth) are fixed at 1.2 V and 180 MHz respectively.
The introduction of a dynamic de-skewing system (DDS) has been tried to enable the power supply voltage and system clock frequency of the audio signal processing block to be switched freely by means of CPU software control. That is to say, since system clock frequency skew occurs at 90 MHz/180 MHz due to switching of the audio signal processing block power supply voltage between 0.9 V and 1.2 V, a dynamic de-skewing system (DDS) has been introduced as a countermeasure to this skew. However, the environment postulated in above Non-patent Document 2 in the prior art is far from a perspective of using Adaptive Voltage Scaling technology effectively for future low-power-consumption implementation.
To date, an effective method has not been proposed as to how to enable function blocks in semiconductor integrated circuit apparatus 40 such as postulated in FIG. 3 freely to vary power supply voltage and system clock frequency on the time axis, and also to exchange data among themselves.
The present invention has been implemented taking into account the points described above, and it is an object of the present invention to provide a semiconductor integrated circuit apparatus that enables function blocks in a semiconductor integrated circuit freely to vary power supply voltage and system clock frequency on the time axis, and also to exchange data among themselves.